A Chaotic IP Watermarking in Physical Layout Level Based on FPGA
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| Format: | Article |
| Source document: | Radioengineering , Vol. 20, No. 1 (2011), s. 118-125 |
| Language: | English |
| Genre/form: | články |
| ISSN: | 1210-2512 |
| Subjects: | |
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